An increase in the speed of data transfer in a semiconductor integrated circuit has been attempted by causing a data signal to be transferred in synchronization with a clock signal between a logic circuit and an SDRAM (Synchronous Dynamic Random Access Memory) which is a semiconductor memory operating in synchronization with a clock signal.
Further, to increase the transfer speed, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) has been increasingly used which outputs data both at the rise and fall of the clock signal.
The output period of read data output by the DDR SDRAM is half the cycle of the clock signal, and thus the data is transferred at a high speed. Meanwhile, a skew between signals is always an issue to be addressed in a parallel interface as used in the DDR SDRAM. Along with the increase in the transfer speed, therefore, it becomes difficult to capture the read data.
Therefore, the DDR SDRAM outputs the read data together with a read data strobe (RDQS) signal synchronized with the read data. That is, the DDR SDRAM outputs the read data in a so-called source synchronous transfer. The logic circuit acquires the read data in accordance with a signal generated from the read data strobe (RDQS) signal. In this configuration, the read data and the read data strobe (RDQS) signal are synchronized with each other. Thus, the phase between the signals becomes substantially constant. Accordingly, the period for defining the read data is not reduced.
Thereafter, to enable the logic circuit to use the read data acquired in accordance with the read data strobe (RDQS) signal, the read data needs to be passed to a storage circuit, such as a flip-flop circuit, which is synchronized with the clock signal.
Therefore, the read data and the read data strobe (RDQS) signal are input to a data terminal and a clock terminal of the flip-flop circuit, respectively, and the read data is latched. Then, the latched data is input to the flip-flop circuit of the next stage. Further, the clock signal used in the logic circuit is input to a clock terminal of the flip-flop circuit, and the latched data is latched.
Herein, it is assumed that a signal line for transmitting the read data strobe (RDQS) signal to the logic circuit is connected to a plurality of semiconductor memories. In this configuration, when the DDR SDRAM outputs the read data strobe (RDQS) signal, the DDR SDRAM drives the signal line for transmitting the read data strobe (RDQS) signal only during the output period of the read data, and does not drive the signal line during the other period. That is, the read data strobe (RDQS) signal is a so-called bus signal. Therefore, the logic of the read data strobe (RDQS) signal is defined during a period of the read data strobe (RDQS) signal effective for receiving the read data, an approximately one cycle period of a logic “L (Low)” preceding the first rise of the read data strobe (RDQS) signal effective for receiving the read data (a so-called read preamble), and an approximately 0.5 cycle period of the logic “L” subsequent to the last fall of the read data strobe (RDQS) signal (a so-called read postamble). In the other period, the read data strobe (RDQS) signal is in a Hi-Z (high impedance) state. In the simple configuration which connects the read data strobe (RDQS) signal to the clock terminal of the flip-flop circuit that latches the read data, therefore, if a pulse coincides with the Hi-Z state of the read data strobe (RDQS) signal when the read data captured in accordance with the read data strobe (RDQS) signal is passed to an internal logic circuit, the captured data may be destroyed.
In view of the above, a semiconductor integrated circuit has been proposed which includes a delay circuit for receiving the input of the read data strobe (RDQS) signal and generating a first timing signal for latching the read data at the flip-flop circuit and a signal defined state maintaining circuit for maintaining, in accordance with a second timing signal generated from the first timing signal, the output from the flip-flop circuit which has latched the read data (e.g., Japanese Laid-open Patent Publication No. 2006-107352). The read data is maintained in the flip-flop circuit for a predetermined period even after the shift of the read data strobe (RDQS) signal to the Hi-Z state. It is therefore possible to ensure a period until the latch of the read data by the flip-flop circuit of the next stage input with the clock signal in the clock terminal thereof. Accordingly, the read data is maintained even if the read data strobe (RDQS) signal falls into the Hi-Z state at the time of inhibiting the input to an input circuit of the read data strobe (RDQS) signal (i.e., at the time of masking).
However, if the read data strobe (RDQS) signal is in the Hi-Z state at the time of permitting the input to the input circuit of the read data strobe (RDQS) signal (i.e., at the time of gating) after the input operation of the read data to the flip-flop circuit has been notified, the flip-flop circuit latches incorrect read data.
As described above, the timing of masking and gating the read data strobe (RDQS) signal deviates from the effective period of the read data strobe (RDQS) signal effective for receiving the read data, the read preamble, and the read postamble for the following reasons. That is, in a period in which the clock signal of the logic circuit is transmitted to the DDR SDRAM and the read data strobe (RDQS) signal is propagated to the logic circuit, a signal delay on the path (i.e., a so-called flight time) is not constant with respect to the timing of masking and gating performed in accordance with the clock signal of the logic circuit, due to a variety of variation factors such as input-output circuit characteristics of the logic circuit, a transmission path delay, and DRAM characteristics. Therefore, the arrival timing of the read data strobe (RDQS) signal to the logic circuit is not constant.
To prevent the flip-flop circuit from latching the incorrect read data, it is conceivable to set the timing of masking and gating the read data strobe (RDQS) signal within the effective period of the read data strobe (RDQS) signal effective for receiving the read data, the read preamble, and the read postamble. However, the signal delay (the flight time) is not constant. Therefore, there arises a case in which the effective period of the read data strobe (RDQS) signal effective for receiving the read data is reduced.
The path for generating the read data strobe (RDQS) signal is constituted by the logic circuit for generating the clock signal, a transmission path of the clock signal, a circuit in the DDR SDRAM for generating the clock signal, a circuit in the DDR SDRAM for generating the read data strobe (RDQS) signal, a transmission path of the read data strobe (RDQS) signal, and a circuit in the logic circuit for receiving the read data strobe (RDQS) signal. Thus, the variation in the amount of the signal delay varies among the respective sections of the path. Accordingly, it is substantially difficult to make the signal delay (the flight time) of the whole path constant.